555 search results - page 46 / 111 » Efficient event-driven simulation of parallel processor arch... |
IPPS
2003
IEEE
15 years 3 months ago
2003
IEEE
The available Instruction Level Parallelism in Java bytecode (Java-ILP) is not readily exploitable using traditional in-order or out-of-order issue mechanisms due to dependencies ...
DATE
2006
IEEE
15 years 4 months ago
2006
IEEE
NoC architectures can be adopted to support general communications among multiple IPs over multi-processor Systems on Chip (SoCs). In this work we illustrate the modeling and simu...
HPCC
2009
Springer
15 years 2 months ago
2009
Springer
This paper studies a load scheduling strategy with nearoptimal processing time leveraging the computational characteristics of parallel DNA sequence alignment algorithms, specific...
IPPS
2005
IEEE
15 years 3 months ago
2005
IEEE
An architecture for a reconfigurable superscalar processor is described in which some of its execution units are implemented in reconfigurable hardware. The overall configuration ...
PPOPP
2006
ACM
15 years 3 months ago
2006
ACM
This work presents a general methodology for estimating the performance of an HPC workload when running on a future hardware architecture. Further, it demonstrates the methodology...