555 search results - page 48 / 111 » Efficient event-driven simulation of parallel processor arch... |
HPCA
1999
IEEE
15 years 2 months ago
1999
IEEE
This work presents and evaluates a novel processor microarchitecture which combines two paradigms: access/ execute decoupling and simultaneous multithreading. We investigate how b...
182
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VLDB
2007
ACM
15 years 10 months ago
2007
ACM
Low-latency and high-throughput processing are key requirements of data stream management systems (DSMSs). Hence, multi-core processors that provide high aggregate processing capa...
CGO
2004
IEEE
15 years 1 months ago
2004
IEEE
To meet the high demand for powerful embedded processors, VLIW architectures are increasingly complex (e.g., multiple clusters), and moreover, they now run increasingly sophistica...
113
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VIS
2007
IEEE
15 years 11 months ago
2007
IEEE
Pipeline architectures provide a versatile and efficient mechanism for constructing visualizations, and they have been implemented in numerous libraries and applications over the p...
IPPS
2006
IEEE
15 years 4 months ago
2006
IEEE
A design process is presented for the selection of a set of instruction set extensions for the PowerPC 405 processor that is embedded into the Xilinx Virtex Family of FPGAs. The i...