555 search results - page 62 / 111 » Efficient event-driven simulation of parallel processor arch... |
MICRO
2005
IEEE
15 years 3 months ago
2005
IEEE
This paper presents an analysis of the performance of the shader processing units in a modern Graphics Processor Unit (GPU) architecture using real graphic applications. The archi...
ISCA
1999
IEEE
15 years 2 months ago
1999
IEEE
In the pursuit of instruction-level parallelism, significant demands are placed on a processor's instruction delivery mechanism. Delivering the performance necessary to meet ...
DAC
2008
ACM
15 years 11 months ago
2008
ACM
Synchronous dataflow (SDF) has been successfully used in design tools for system-level simulation of wireless communication systems. Modern wireless communication standards involv...
CLUSTER
2007
IEEE
15 years 4 months ago
2007
IEEE
— The Cell Broadband Engine (BE) is a heterogeneous multicore processor, combining a general-purpose POWER architecture core with eight independent single-instructionmultiple-dat...
ASPDAC
1998
ACM
15 years 2 months ago
1998
ACM
We developed a new modular synthesis approach for design of low-power core-based data-intensive application-specific systems on silicon. The power optimization is conducted in th...