555 search results - page 62 / 111 » Efficient event-driven simulation of parallel processor arch... |
109
click to vote
MICRO
2005
IEEE
15 years 7 months ago
2005
IEEE
This paper presents an analysis of the performance of the shader processing units in a modern Graphics Processor Unit (GPU) architecture using real graphic applications. The archi...
118
click to vote
ISCA
1999
IEEE
15 years 6 months ago
1999
IEEE
In the pursuit of instruction-level parallelism, significant demands are placed on a processor's instruction delivery mechanism. Delivering the performance necessary to meet ...
118
click to vote
DAC
2008
ACM
16 years 3 months ago
2008
ACM
Synchronous dataflow (SDF) has been successfully used in design tools for system-level simulation of wireless communication systems. Modern wireless communication standards involv...
124
click to vote
CLUSTER
2007
IEEE
15 years 8 months ago
2007
IEEE
— The Cell Broadband Engine (BE) is a heterogeneous multicore processor, combining a general-purpose POWER architecture core with eight independent single-instructionmultiple-dat...
120
click to vote
ASPDAC
1998
ACM
15 years 6 months ago
1998
ACM
We developed a new modular synthesis approach for design of low-power core-based data-intensive application-specific systems on silicon. The power optimization is conducted in th...