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» Elements of low power design for integrated systems
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DSD
2007
IEEE
160views Hardware» more  DSD 2007»
15 years 8 months ago
Alternatives in Designing Level-Restoring Buffers for Interconnection Networks in Field-Programmable Gate Arrays
Programmable routing and logic in field-programmable gate arrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the ...
Scott Miller, Mihai Sima, Michael McGuire
ATS
1998
IEEE
112views Hardware» more  ATS 1998»
15 years 6 months ago
Integrated Current Sensing Device for Micro IDDQ Test
A current sensing device, namely Hall Effect MOSFET (HEMOS) is proposed. It is experimentally shown that the HEMOS enables a non-contacting, and non-disturbing current measurement...
Koichi Nose, Takayasu Sakurai
INTEGRATION
2008
183views more  INTEGRATION 2008»
15 years 1 months ago
Network-on-Chip design and synthesis outlook
With the growing complexity in consumer embedded products, new tendencies forecast heterogeneous Multi-Processor SystemsOn-Chip (MPSoCs) consisting of complex integrated component...
David Atienza, Federico Angiolini, Srinivasan Mura...
DAC
2004
ACM
16 years 2 months ago
FPGA power reduction using configurable dual-Vdd
Power optimization is of growing importance for FPGAs in nanometer technologies. Considering dual-Vdd technique, we show that configurable power supply is required to obtain a sat...
Fei Li, Yan Lin, Lei He
SIGUCCS
2003
ACM
15 years 7 months ago
Integrating WebCT with diverse campus systems
The University of Delaware has a powerful legacy SIS system. The University plans to replace this system in 2004-05. In the meantime, we have populated WebCT rosters using custom ...
Jeff Whisler