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DAC
2005
ACM
14 years 7 months ago
Hardware speech recognition for user interfaces in low cost, low power devices
We propose a system architecture for real-time hardware speech recognition on low-cost, power-constrained devices. The system is intended to support real-time speech-based user in...
Sergiu Nedevschi, Rabin K. Patra, Eric A. Brewer
ETS
2006
IEEE
106views Hardware» more  ETS 2006»
14 years 12 days ago
"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC
In this paper, complex mixed signal circuits such as SiP or SOC including several ADCs and DACs are considered. A new DFT technique is proposed allowing the test of this complete ...
Vincent Kerzerho, Philippe Cauvet, Serge Bernard, ...
ISSTA
2006
ACM
14 years 9 days ago
Architecture-driven platform independent deterministic replay for distributed hard real-time systems
Distributed hard real-time systems have become a major component of many advanced technical products. Means to ensure their proper quality are thus of paramount importance. To ens...
Holger Giese, Stefan Henkler
ITC
1996
IEEE
98views Hardware» more  ITC 1996»
13 years 10 months ago
Mixed-Mode BIST Using Embedded Processors
Abstract. In complex systems, embedded processors may be used to run software routines for test pattern generation and response evaluation. For system components which are not comp...
Sybille Hellebrand, Hans-Joachim Wunderlich, Andre...
ET
2002
72views more  ET 2002»
13 years 6 months ago
Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor
Abstract. A novel approach for using an embedded processor to aid in deterministic testing of the other components of a system-on-a-chip (SOC) is presented. The tester loads a prog...
Abhijit Jas, Nur A. Touba