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142
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DATE
2004
IEEE
149views Hardware» more  DATE 2004»
15 years 8 months ago
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
This paper describes a novel design methodology to implement a secure DPA resistant crypto processor. The methodology is suitable for integration in a common automated standard ce...
Kris Tiri, Ingrid Verbauwhede
158
Voted
DAC
2010
ACM
15 years 8 months ago
Quality metric evaluation of a physical unclonable function derived from an IC's power distribution system
The level of security provided by digital rights management functions and cryptographic protocols depend heavily on the security of an embedded secret key. The current practice of...
Ryan Helinski, Dhruva Acharyya, Jim Plusquellic
SEUS
2009
IEEE
15 years 11 months ago
A Single-Path Chip-Multiprocessor System
Abstract. In this paper we explore the combination of a time-predictable chipmultiprocessor system with the single-path programming paradigm. Time-sliced arbitration of the main me...
Martin Schoeberl, Peter P. Puschner, Raimund Kirne...
ICESS
2007
Springer
15 years 11 months ago
Memory Offset Assignment for DSPs
Compact code generation is very important for an embedded system that has to be implemented on a chip with a severely limited amount of size. Even though on-chip data memory optimi...
Jinpyo Hong, J. Ramanujam
ECRTS
1999
IEEE
15 years 9 months ago
An approach to task attribute assignment for uniprocessor systems
The purpose of this paper is to investigate the issues related to task attribute assignment on an individual processor. The majority of papers on fixed priority scheduling make th...
Iain Bate, Alan Burns