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CLUSTER
2008
IEEE
16 years 22 days ago
Intelligent compilers
—The industry is now in agreement that the future of architecture design lies in multiple cores. As a consequence, all computer systems today, from embedded devices to petascale ...
John Cavazos
IEEEPACT
2007
IEEE
16 years 17 days ago
Error Detection Using Dynamic Dataflow Verification
Continued scaling of CMOS technology to smaller transistor sizes makes modern processors more susceptible to both transient and permanent hardware faults. Circuitlevel techniques ...
Albert Meixner, Daniel J. Sorin
ISSAC
2007
Springer
132views Mathematics» more  ISSAC 2007»
16 years 12 days ago
Adaptive loops with kaapi on multicore and grid: applications in symmetric cryptography
The parallelization of two applications in symmetric cryptography is considered: block ciphering and a new method based on random sampling for the selection of basic substitution ...
Vincent Danjean, Roland Gillard, Serge Guelton, Je...
IPPS
2006
IEEE
16 years 8 days ago
An adaptive system-on-chip for network applications
This paper presents the hardware architecture of DynaCORE, a dynamically reconfigurable system-on-chip for network applications. DynaCORE is an application specific coprocessor ...
Roman Koch, Thilo Pionteck, Carsten Albrecht, Erik...
ECRTS
2005
IEEE
15 years 12 months ago
A WCET-Oriented Static Branch Prediction Scheme for Real Time Systems
Branch prediction mechanisms are becoming commonplace within current generation processors. Dynamic branch predictors, albeit able to predict branches quite accurately in average,...
François Bodin, Isabelle Puaut