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DATE
2008
IEEE
115views Hardware» more  DATE 2008»
15 years 11 months ago
Improving the Efficiency of Run Time Reconfigurable Devices by Configuration Locking
Run-time reconfigurable logic is a very attractive alterative in the design of SoC. However, configuration overhead can largely decrease the system performance. In this work, we p...
Yang Qu, Juha-Pekka Soininen, Jari Nurmi
RTAS
2008
IEEE
15 years 11 months ago
TOSSTI: Saving Time and Energy in TinyOS with Software Thread Integration
Many wireless sensor nodes (motes) interface with slow peripheral devices, requiring the processor to wait. These delays waste time, energy and power, which are valuable but limit...
Zane D. Purvis, Alexander G. Dean
DATE
2007
IEEE
110views Hardware» more  DATE 2007»
15 years 11 months ago
Reconfigurable system-on-chip data processing units for space imaging instruments
Individual Data Processing Units (DPUs) are commonly used for operational control and specific data processing of scientific space instruments. To overcome the limitations of trad...
Björn Fiethe, Harald Michalik, C. Dierker, Bj...
IPPS
2007
IEEE
15 years 11 months ago
A CAM Emulator Using Look-Up Table Cascades
An address table relates k different registered vectors to the addresses from 1 to k. An address generation function represents the address table. This paper presents a realizatio...
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
IPPS
2007
IEEE
15 years 11 months ago
Splice: A Standardized Peripheral Logic and Interface Creation Engine
Recent advancements in FPGA technology have allowed manufacturers to place general-purpose processors alongside user-configurable logic gates on a single chip. At first glance, ...
Justin Thiel, Ron K. Cytron