Sciweavers

1042 search results - page 79 / 209
» Embedded Systems Design: Optimization Challenges
Sort
View
132
Voted
HPCA
1996
IEEE
15 years 7 months ago
Co-Scheduling Hardware and Software Pipelines
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded process...
Ramaswamy Govindarajan, Erik R. Altman, Guang R. G...
150
Voted
CASES
2005
ACM
15 years 5 months ago
Exploring the design space of LUT-based transparent accelerators
Instruction set customization accelerates the performance of applications by compressing the length of critical dependence paths and reducing the demands on processor resources. W...
Sami Yehia, Nathan Clark, Scott A. Mahlke, Kriszti...
EMSOFT
2005
Springer
15 years 8 months ago
A unified HW/SW interface model to remove discontinuities between HW and SW design
One major challenge in System-on-Chip (SoC) design is the definition and design of interfaces between hardware and software. Traditional ASIC designer and software designer model ...
Aimen Bouchhima, Xi Chen, Frédéric P...
CODES
2000
IEEE
15 years 7 months ago
Towards a new standard for system-level design
—Huge new design challenges for system-on-chip (SoC) are the result of decreasing time-to-market coupled with rapidly increasing gate counts and embedded software representing 50...
Stan Y. Liao
114
Voted
CASES
2006
ACM
15 years 9 months ago
Memory optimization by counting points in integer transformations of parametric polytopes
Memory size reduction and memory accesses optimization are crucial issues for embedded systems. In the context of affine programs, these two challenges are classically tackled by ...
Rachid Seghir, Vincent Loechner