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DATE
2007
IEEE
99views Hardware» more  DATE 2007»
15 years 8 months ago
Instruction trace compression for rapid instruction cache simulation
Modern Application Specific Instruction Set Processors (ASIPs) have customizable caches, where the size, associativity and line size can all be customized to suit a particular ap...
Andhi Janapsatya, Aleksandar Ignjatovic, Sri Param...
130
Voted
HASKELL
2006
ACM
15 years 7 months ago
Strong types for relational databases
Haskell’s type system with multi-parameter constructor classes and functional dependencies allows static (compile-time) computations to be expressed by logic programming on the ...
Alexandra Silva, Joost Visser
106
Voted
JAVA
2000
Springer
15 years 5 months ago
HBench: Java: an application-specific benchmarking framework for Java virtual machines
Java applications represent a broad class of programs, ranging from programs running on embedded products to highperformance server applications. Standard Java benchmarks ignore t...
Xiaolan Zhang, Margo I. Seltzer
FCCM
2000
IEEE
122views VLSI» more  FCCM 2000»
15 years 6 months ago
Evaluating Hardware Compilation Techniques
Hardware compilation techniques which use highlevel programming languages to describe and synthesize hardware are gaining popularity. They are especially useful for reconfigurable...
Markus Weinhardt, Wayne Luk
LCTRTS
2009
Springer
15 years 8 months ago
A compiler optimization to reduce soft errors in register files
Register file (RF) is extremely vulnerable to soft errors, and traditional redundancy based schemes to protect the RF are prohibitive not only because RF is often in the timing c...
Jongeun Lee, Aviral Shrivastava