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VLSID
2009
IEEE
96views VLSI» more  VLSID 2009»
16 years 6 months ago
Efficient Placement of Compressed Code for Parallel Decompression
Code compression is important in embedded systems design since it reduces the code size (memory requirement) and thereby improves overall area, power and performance. Existing res...
Xiaoke Qin, Prabhat Mishra
VLSID
2009
IEEE
170views VLSI» more  VLSID 2009»
16 years 6 months ago
Code Transformations for TLB Power Reduction
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivasta...
CHES
2009
Springer
230views Cryptology» more  CHES 2009»
16 years 6 months ago
Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves
Abstract. This paper presents a design-space exploration of an applicationspecific instruction-set processor (ASIP) for the computation of various cryptographic pairings over Barre...
David Kammler, Diandian Zhang, Dominik Auras, Gerd...
ICCD
2004
IEEE
111views Hardware» more  ICCD 2004»
16 years 2 months ago
Power-Aware Deterministic Block Allocation for Low-Power Way-Selective Cache Structure
This paper proposes a power-aware cache block allocation algorithm for the way-selective setassociative cache on embedded systems to reduce energy consumption without additional d...
Jung-Wook Park, Gi-Ho Park, Sung-Bae Park, Shin-Du...
ICCD
2001
IEEE
124views Hardware» more  ICCD 2001»
16 years 2 months ago
High-Level Power Modeling of CPLDs and FPGAs
In this paper, we present a high-level power modeling technique to estimate the power consumption of reconfigurable devices such as complex programmable logic devices (CPLDs) and ...
Li Shang, Niraj K. Jha