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GLVLSI
2010
IEEE
187views VLSI» more  GLVLSI 2010»
15 years 8 months ago
Write activity reduction on flash main memory via smart victim cache
Flash Memory is a desirable candidate for main memory replacement in embedded systems due to its low leakage power consumption, higher density and non-volatility characteristics. ...
Liang Shi, Chun Jason Xue, Jingtong Hu, Wei-Che Ts...
131
Voted
JTRES
2009
ACM
15 years 8 months ago
A technology compatibility kit for safety critical Java
Safety Critical Java is a specification being built on top a subset of interfaces from the Real-Time Specification for Java. It is designed to ease development and analysis of s...
Lei Zhao, Daniel Tang, Jan Vitek
116
Voted
VLSID
1999
IEEE
99views VLSI» more  VLSID 1999»
15 years 7 months ago
Array Index Allocation under Register Constraints in DSP Programs
Abstract Code optimization for digital signal processors DSPs has been identi ed as an important new topic in system-level design of embedded systems. Both DSP processors and algor...
Anupam Basu, Rainer Leupers, Peter Marwedel
140
Voted
GLVLSI
1998
IEEE
122views VLSI» more  GLVLSI 1998»
15 years 7 months ago
Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding
With the increased clock frequency of modern, high-performance processors over 500 MHz, in some cases, limiting the power dissipation has become the most stringent design target. ...
Luca Benini, Giovanni De Micheli, Alberto Macii, E...
124
Voted
ISORC
1998
IEEE
15 years 7 months ago
The Time-Triggered Architecture
The Time-Triggered Architecture (TTA) provides a computing infrastructure for the design and implementation of dependable distributed embedded systems. A large real-time applicatio...
Hermann Kopetz