7 search results - page 1 / 2 » Embedded tutorial: formal equivalence checking between syste... |
74
Voted
ICCAD
2005
IEEE
15 years 3 months ago
2005
IEEE
75
Voted
MEMOCODE
2007
IEEE
15 years 4 months ago
2007
IEEE
The always increasing complexity of digital system is overcome in design flows based on Transaction Level Modeling (TLM) by designing and verifying the system at difbstraction le...
108
Voted
DAC
2007
ACM
15 years 2 months ago
2007
ACM
When designers create RTL models from a system-level specification, arrays in the system-level model are often implemented as memories in the RTL. Knowing the correspondence betwe...
DAC
2006
ACM
15 years 11 months ago
2006
ACM
Ever-growing complexity is forcing design to move above RTL. For example, golden functional models are being written as clearly as possible in software and not optimized or intend...
102
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DAC
1996
ACM
15 years 2 months ago
1996
ACM
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional pr...