The always increasing complexity of digital system is overcome in design flows based on Transaction Level Modeling (TLM) by designing and verifying the system at difbstraction le...
When designers create RTL models from a system-level specification, arrays in the system-level model are often implemented as memories in the RTL. Knowing the correspondence betwe...
Ever-growing complexity is forcing design to move above RTL. For example, golden functional models are being written as clearly as possible in software and not optimized or intend...
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional pr...