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ASPLOS
2000
ACM
15 years 9 months ago
FLASH vs. (Simulated) FLASH: Closing the Simulation Loop
Simulation is the primary method for evaluating computer systems during all phases of the design process. One significant problem with simulation is that it rarely models the syst...
Jeff Gibson, Robert Kunz, David Ofelt, Mark Heinri...
PPOPP
1999
ACM
15 years 9 months ago
Automatic Parallelization of Divide and Conquer Algorithms
Divide and conquer algorithms are a good match for modern parallel machines: they tend to have large amounts of inherent parallelism and they work well with caches and deep memory...
Radu Rugina, Martin C. Rinard
ICS
1999
Tsinghua U.
15 years 9 months ago
Clustered speculative multithreaded processors
In this paper we present a processor microarchitecture that can simultaneously execute multiple threads and has a clustered design for scalability purposes. A main feature of the ...
Pedro Marcuello, Antonio González
HPCA
1998
IEEE
15 years 9 months ago
Speculative Versioning Cache
Dependences among loads and stores whose addresses are unknown hinder the extraction of instruction level parallelism during the execution of a sequential program. Such ambiguous ...
Sridhar Gopal, T. N. Vijaykumar, James E. Smith, G...
PLDI
1998
ACM
15 years 9 months ago
Improving Performance by Branch Reordering
The conditional branch has long been considered an expensive operation. The relative cost of conditional branches has increased as recently designed machines are now relying on de...
Minghui Yang, Gang-Ryung Uh, David B. Whalley