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76
Voted
IPPS
2009
IEEE
15 years 4 months ago
2009
IEEE
DFT
2006
IEEE
15 years 3 months ago
2006
IEEE
This paper1 discusses a defect tolerant and energy economized computing array for the DSP plane of a 3-D Heterogeneous System on a Chip. We present the J-platform, which employs c...