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    ARC
    2008
    Springer
    99views Hardware» more  ARC 2008»
    Physical Design of FPGA Interconnect to Prevent Information Leakage
    14 years 11 months ago
    Physical Design of FPGA Interconnect to Prevent Information Leakage
    Download  www.tsi.enst.fr
    Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogv...
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    DATE
    2007
    IEEE
    150views Hardware» more  DATE 2007»
    Assessing carbon nanotube bundle interconnect for future FPGA architectures
    15 years 3 months ago
    Assessing carbon nanotube bundle interconnect for future FPGA architectures
    Download  www.cse.psu.edu
    Field Programmable Gate Arrays (FPGAs) are important hardware platforms in various applications due to increasing design complexity and mask costs. However, as CMOS process techno...
    Soumya Eachempati, Arthur Nieuwoudt, Aman Gayasen,...
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    FPGA
    2005
    ACM
    122views FPGA» more  FPGA 2005»
    Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability
    15 years 3 months ago
    Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability
    Download  eda.ee.ucla.edu
    Vdd-programmable FPGAs have been proposed recently to reduce FPGA power, where Vdd levels can be customized for different circuit elements and unused circuit elements can be powe...
    Yan Lin, Fei Li, Lei He
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    FPGA
    2005
    ACM
    156views FPGA» more  FPGA 2005»
    Design of programmable interconnect for sublithographic programmable logic arrays
    15 years 3 months ago
    Design of programmable interconnect for sublithographic programmable logic arrays
    Download  ic.ese.upenn.edu
    Sublithographic Programmable Logic Arrays can be interconnected and restored using nanoscale wires. Building on a hybrid of bottom-up assembly techniques supported by conventional...
    André DeHon
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    FPGA
    2009
    ACM
    150views FPGA» more  FPGA 2009»
    Bus mastering PCI express in an FPGA
    15 years 4 months ago
    Bus mastering PCI express in an FPGA
    Download  research.microsoft.com
    This paper describes a bus mastering implementation of the PCI Express protocol using a Xilinx FPGA. While the theoretical peak performance of PCI Express is quite high, attaining...
    Ray Bittner
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