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CGO
2004
IEEE
15 years 8 months ago
Custom Data Layout for Memory Parallelism
In this paper, we describe a generalized approach to deriving a custom data layout in multiple memory banks for array-based computations, to facilitate high-bandwidth parallel mem...
Byoungro So, Mary W. Hall, Heidi E. Ziegler
CGO
2004
IEEE
15 years 8 months ago
A Compiler Scheme for Reusing Intermediate Computation Results
Recent research has shown that programs often exhibit value locality. Such locality occurs when a code segment, although executed repeatedly in the program, takes only a small num...
Yonghua Ding, Zhiyuan Li
CGO
2004
IEEE
15 years 8 months ago
VHC: Quickly Building an Optimizer for Complex Embedded Architectures
To meet the high demand for powerful embedded processors, VLIW architectures are increasingly complex (e.g., multiple clusters), and moreover, they now run increasingly sophistica...
Michael Dupré, Nathalie Drach, Olivier Tema...
CGO
2004
IEEE
15 years 8 months ago
A Dynamically Tuned Sorting Library
Empirical search is a strategy used during the installation of library generators such as ATLAS, FFTW, and SPIRAL to identify the algorithm or the version of an algorithm that del...
Xiaoming Li, María Jesús Garzar&aacu...
CODES
2004
IEEE
15 years 8 months ago
A loop accelerator for low power embedded VLIW processors
The high transistor density afforded by modern VLSI processes have enabled the design of embedded processors that use clustered execution units to deliver high levels of performan...
Binu K. Mathew, Al Davis
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