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140
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DATE
2003
IEEE
127views Hardware» more  DATE 2003»
15 years 10 months ago
Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology
In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...
Amit Agarwal, Kaushik Roy, T. N. Vijaykumar
ISCA
1999
IEEE
187views Hardware» more  ISCA 1999»
15 years 9 months ago
Area Efficient Architectures for Information Integrity in Cache Memories
Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it...
Seongwoo Kim, Arun K. Somani
151
Voted
DBPL
1999
Springer
98views Database» more  DBPL 1999»
15 years 9 months ago
Ozone: Integrating Structured and Semistructured Data
Applications have an increasing need to manage semistructured data such as data encoded in XML along with conventional structured data. We extend the structured object database ...
Tirthankar Lahiri, Serge Abiteboul, Jennifer Widom
VISUALIZATION
1998
IEEE
15 years 9 months ago
Large scale terrain visualization using the restricted quadtree triangulation
Real-time rendering of triangulated surfaces has attracted growing interest in the last few years. However, interactive visualization of very large scale grid digital elevation mo...
Renato Pajarola
DAC
1996
ACM
15 years 9 months ago
Address Calculation for Retargetable Compilation and Exploration of Instruction-Set Architectures
The advent of parallel executing Address Calculation Units (ACUs) in Digital Signal Processor (DSP) and Application Specific InstructionSet Processor (ASIP) architectures has made...
Clifford Liem, Pierre G. Paulin, Ahmed Amine Jerra...