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HPCA
2007
IEEE
15 years 10 months ago
A Scalable, Non-blocking Approach to Transactional Memory
Transactional Memory (TM) provides mechanisms that promise to simplify parallel programming by eliminating the need for locks and their associated problems (deadlock, livelock, pr...
Hassan Chafi, Jared Casper, Brian D. Carlstrom, Au...
MICRO
1999
IEEE
108views Hardware» more  MICRO 1999»
15 years 2 months ago
Exploiting ILP in Page-based Intelligent Memory
This study compares the speed, area, and power of di erent implementations of Active Pages OCS98], an intelligent memory system which helps bridge the growing gap between processo...
Mark Oskin, Justin Hensley, Diana Keen, Frederic T...
SIGCOMM
1995
ACM
15 years 1 months ago
Pipelined Memory Shared Buffer for VLSI Switches
ABSTRACT: Switch chips are building blocks for computer and communication systems. Switches need internal buffering, because of output contention; shared buffering is known to perf...
Manolis Katevenis, Panagiota Vatsolaki, Aristides ...
IPPS
2007
IEEE
15 years 4 months ago
A Key-based Adaptive Transactional Memory Executor
Software transactional memory systems enable a programmer to easily write concurrent data structures such as lists, trees, hashtables, and graphs, where non-conflicting operation...
Tongxin Bai, Xipeng Shen, Chengliang Zhang, Willia...
JCISE
2002
117views more  JCISE 2002»
14 years 9 months ago
Memory Analysis of Solid Model Representations for Heterogeneous Objects
Methods to represent and exchange parts consisting of Functionally Graded Material (FGM) for Solid Freeform Fabrication (SFF) with Local Composition Control (LCC) are evaluated ba...
Todd R. Jackson, Wonjoon Cho, Nicholas M. Patrikal...