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» Equivalence checking for behaviorally synthesized pipelines
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DAC
2012
ACM
11 years 6 months ago
Equivalence checking for behaviorally synthesized pipelines
Loop pipelining is a critical transformation in behavioral synthesis. It is crucial to producing hardware designs with acceptable latency and throughput. However, it is a complex ...
Kecheng Hao, Sandip Ray, Fei Xie
DATE
2010
IEEE
163views Hardware» more  DATE 2010»
13 years 9 months ago
Optimizing equivalence checking for behavioral synthesis
Abstract—Behavioral synthesis is the compilation of an Electronic system-level (ESL) design into an RTL implementation. We present a suite of optimizations for equivalence checki...
Kecheng Hao, Fei Xie, Sandip Ray, Jin Yang
MTV
2003
IEEE
109views Hardware» more  MTV 2003»
13 years 9 months ago
A Methodology for Validation of Microprocessors using Equivalence Checking
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. ...
Prabhat Mishra, Nikil D. Dutt
TVLSI
2008
151views more  TVLSI 2008»
13 years 4 months ago
Guest Editorial Special Section on Design Verification and Validation
ion levels. The framework also supports the generation of test constraints, which can be satisfied using a constraint solver to generate tests. A compositional verification approac...
I. Harris, D. Pradhan
PLDI
2009
ACM
13 years 11 months ago
Proving optimizations correct using parameterized program equivalence
Translation validation is a technique for checking that, after an optimization has run, the input and output of the optimization are equivalent. Traditionally, translation validat...
Sudipta Kundu, Zachary Tatlock, Sorin Lerner