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99
Voted
VTS
2006
IEEE
93views Hardware» more  VTS 2006»
15 years 6 months ago
Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring
A new algorithm for identifying stuck faults in combinational circuits that cannot be detected by a given input sequence is presented. Other than pre and post-processing steps, ce...
Vishwani D. Agrawal, Soumitra Bose, Vijay Gangaram
107
Voted
DAC
1997
ACM
15 years 5 months ago
Power Macromodeling for High Level Power Estimation
A modeling approach is presented that captures the dependence of the power dissipation of a combinational logic circuit on its input output signal switching activity. The resulting...
Subodh Gupta, Farid N. Najm
129
Voted
DAC
1994
ACM
15 years 5 months ago
Exact and Approximate Methods for Calculating Signal and Transition Probabilities in FSMs
In this paper, we consider the problem of calculating the signal and transition probabilities of the internal nodes of the combinational logic part of a nite state machine (FSM). ...
Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
DFG
2004
Springer
15 years 4 months ago
Verification of PLC Programs Given as Sequential Function Charts
Programmable Logic Controllers (PLC) are widespread in the manufacturing and processing industries to realize sequential procedures and to avoid safety-critical states. For the spe...
Nanette Bauer, Sebastian Engell, Ralf Huuck, Sven ...
112
Voted
FDTC
2006
Springer
117views Cryptology» more  FDTC 2006»
15 years 4 months ago
DPA on Faulty Cryptographic Hardware and Countermeasures
Abstract. Balanced gates are an effective countermeasure against power analysis attacks only if they can be guaranteed to maintain their power balance. Traditional testing and reli...
Konrad J. Kulikowski, Mark G. Karpovsky, Alexander...