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ICASSP
2008
IEEE
15 years 7 months ago
Accurate models for estimating area and power of FPGA implementations
This paper presents accurate area and power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family. These models are designed to facilitate efficien...
Lanping Deng, Kanwaldeep Sobti, Chaitali Chakrabar...
97
Voted
DATE
2000
IEEE
108views Hardware» more  DATE 2000»
15 years 5 months ago
A 50 Mbit/s Iterative Turbo-Decoder
Very low bit error rate has become an important constraint in high performance communication systems that operate at very low signal to noise ratios: due to their impressive codin...
F. Viglione, Guido Masera, Gianluca Piccinini, Mas...
103
Voted
MM
1998
ACM
79views Multimedia» more  MM 1998»
15 years 5 months ago
Organizing Multicast Receivers Deterministically by Packet-Loss Correlation
The ability to trace multicast paths is currently available in the Internet by means of IGMP MTRACE packets. We introduce Tracer, the rst protocol that organizes the receivers of ...
Brian Neil Levine, Sanjoy Paul, J. J. Garcia-Luna-...
EDCC
2008
Springer
15 years 2 months ago
Practical Setup Time Violation Attacks on AES
Faults attacks are a powerful tool to break some implementations of robust cryptographic algorithms such as AES [8] and DES [3]. Various methods of faults attack on cryptographic ...
Nidhal Selmane, Sylvain Guilley, Jean-Luc Danger
80
Voted
SIGCSE
2008
ACM
138views Education» more  SIGCSE 2008»
15 years 22 days ago
Debugging: the good, the bad, and the quirky -- a qualitative analysis of novices' strategies
A qualitative analysis of debugging strategies of novice Java programmers is presented. The study involved 21 CS2 students from seven universities in the U.S. and U.K. Subjects &q...
Laurie Murphy, Gary Lewandowski, Renée McCa...