Sciweavers

381 search results - page 50 / 77
» Error-Correcting Codes in Steganography
Sort
View
ISCA
2010
IEEE
336views Hardware» more  ISCA 2010»
15 years 6 months ago
Reducing cache power with low-cost, multi-bit error-correcting codes
Technology advancements have enabled the integration of large on-die embedded DRAM (eDRAM) caches. eDRAM is significantly denser than traditional SRAMs, but must be periodically r...
Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chisht...
TON
2012
13 years 4 months ago
A Transport Protocol to Exploit Multipath Diversity in Wireless Networks
Abstract—Wireless networks (including wireless mesh networks) provide opportunities for using multiple paths. Multihoming of hosts, possibly using different technologies and prov...
Vicky Sharma, Koushik Kar, K. K. Ramakrishnan, Shi...
ICMCS
2006
IEEE
98views Multimedia» more  ICMCS 2006»
15 years 8 months ago
Unequal Iterative Decoding for Power Efficient Video Transmission
We present an unequal iterative decoding (UID) approach for minimization of the receiver power consumption subject to a given quality of service, by exploiting data partitioning a...
Yongfang Wang, Songyu Yu, Xiaokang Yang
ISCA
2009
IEEE
148views Hardware» more  ISCA 2009»
15 years 8 months ago
Memory mapped ECC: low-cost error protection for last level caches
This paper presents a novel technique, Memory Mapped ECC, which reduces the cost of providing error correction for SRAM caches. It is important to limit such overheads as processo...
Doe Hyun Yoon, Mattan Erez
ISCA
2011
IEEE
522views Hardware» more  ISCA 2011»
14 years 5 months ago
CPPC: correctable parity protected cache
Due to shrinking feature sizes processors are becoming more vulnerable to soft errors. Write-back caches are particularly vulnerable since they hold dirty data that do not exist i...
Mehrtash Manoochehri, Murali Annavaram, Michel Dub...