710 search results - page 41 / 142 » Estimating design time for system circuits |
ICCD
2008
IEEE
15 years 8 months ago
2008
IEEE
— This paper looks at designing circuit elements that will be constructed with nanoscale magnets within the Quantum-dot Cellular Automata (QCA) computational paradigm. In magneti...
114
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DAC
2006
ACM
16 years 24 days ago
2006
ACM
Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...
109
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DAC
2006
ACM
16 years 24 days ago
2006
ACM
Existing approaches to timing analysis under uncertainty are based on restrictive assumptions. Statistical STA techniques assume that the full probabilistic distribution of parame...
ISCAS
2006
IEEE
15 years 5 months ago
2006
IEEE
Abstract— This paper introduces a novel four-order system, which can generate one-directional (1-D) n−torus, twodirectional (2-D) n × m −torus, three-directional (3-D) n × ...
110
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CSREAESA
2003
15 years 1 months ago
2003
We present an approach for Worst-Case Execution Time (WCET) Analysis of embedded system software, that is generated from Petri net specifications. The presented approach is part ...