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» Estimating design time for system circuits
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DATE
2010
IEEE
180views Hardware» more  DATE 2010»
15 years 5 months ago
Reliability- and process variation-aware placement for FPGAs
Abstract—Negative bias temperature instability (NBTI) significantly affects nanoscale integrated circuit performance and reliability. The degradation in threshold voltage (Vth) d...
Assem A. M. Bsoul, Naraig Manjikian, Li Shang
TSP
2008
118views more  TSP 2008»
14 years 11 months ago
Channel-Aware Random Access Control for Distributed Estimation in Sensor Networks
A cross-layered slotted ALOHA protocol is proposed and analyzed for distributed estimation in sensor networks. Suppose that the sensors in the network record local measurements of ...
Y.-W. P. Hong, Keng-U Lei, Chong-Yung Chi
ISORC
1999
IEEE
15 years 4 months ago
Implementing the Real-Time Publisher/Subscriber Model on the Controller Area Network (CAN)
Designing distributed real-time systems as being composed of communicating objects offers many advantages with respect to modularity and extensibility of these systems. However, d...
Jörg Kaiser, Michael Mock
ICC
2007
IEEE
15 years 6 months ago
Joint Transmitter-Receiver Beamforming Over Space-Time Fading Channels
Abstract—The problem of joint transmitter and receiver beamforming in the downlink DS-CDMA over multipath fading channels is considered in this paper. The proposed investigation ...
Tingting Zhang, Athanassios Manikas
ISSS
2002
IEEE
106views Hardware» more  ISSS 2002»
15 years 4 months ago
Modeling Assembly Instruction Timing in Superscalar Architectures
This paper proposes an original model of the execution time of assembly instructions in superscalar architectures. The approach is based on a rigorous mathematical model and provi...
William Fornaciari, Vito Trianni, Carlo Brandolese...