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123
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ATS
2003
IEEE
110views Hardware» more  ATS 2003»
15 years 7 months ago
Chip-Level Diagnostic Strategy for Full-Scan Designs with Multiple Faults
Fault diagnosis of full-scan designs has been progressed significantly. However, most existing techniques are aimed at a logic block with a single fault. Strategies on top of thes...
Yu-Chiun Lin, Shi-Yu Huang
112
Voted
GLVLSI
2003
IEEE
152views VLSI» more  GLVLSI 2003»
15 years 7 months ago
Dynamic single-rail self-timed logic structures for power efficient synchronous pipelined designs
The realization of fast datapaths in signal processing environments requires fastest, power efficient logic styles with synchronous behavior. This paper presents a method to combi...
Frank Grassert, Dirk Timmermann
123
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SBCCI
2003
ACM
213views VLSI» more  SBCCI 2003»
15 years 7 months ago
Algorithms and Tools for Network on Chip Based System Design
Network on Chip (NoC) is a new paradigm for designing core based System on Chips. It supports high degree of reusability and is scalable. In this paper, an efficient Two-Step Gene...
Tang Lei, Shashi Kumar
GLOBECOM
2010
IEEE
14 years 12 months ago
Interference-Aware Robust Wireless Mesh Network Design
Interference has been proven to have an effect on the performance in wireless mesh networks (WMN). Using multichannels can improve the performance of WMNs by reducing interference ...
Farah Kandah, Weiyi Zhang, Yashaswi Singh, Juan Li
HCI
2009
14 years 11 months ago
User Centered Design of a Learning Object Repository
This work outlines the design process of a user centered learning object repository. A repository should foster the development and acquisition of both generic and specific informa...
Núria Ferran, Ana-Elena Guerrero-Rold&aacut...