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DATE
2008
IEEE
145views Hardware» more  DATE 2008»
15 years 8 months ago
Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures
We present a novel methodology for design space exploration using a two-steps scheme to optimize the number of virtual channel buffers (buffers take the premier share of the route...
Mohammad Abdullah Al Faruque, Jörg Henkel
PPOPP
2006
ACM
15 years 7 months ago
Exploiting distributed version concurrency in a transactional memory cluster
We investigate a transactional memory runtime system providing scaling and strong consistency for generic C++ and SQL applications on commodity clusters. We introduce a novel page...
Kaloian Manassiev, Madalin Mihailescu, Cristiana A...
DTJ
1998
171views more  DTJ 1998»
15 years 1 months ago
Measurement and Analysis of C and C++ Performance
ir increasing use of abstraction, modularity, delayed binding, polymorphism, and source reuse, especially when these attributes are used in combination. Modern processor architectu...
Hemant G. Rotithor, Kevin W. Harris, Mark W. Davis
TC
2011
14 years 8 months ago
Software-Based Cache Coherence with Hardware-Assisted Selective Self-Invalidations Using Bloom Filters
— Implementing shared memory consistency models on top of hardware caches gives rise to the well-known cache coherence problem. The standard solution involves implementing cohere...
Thomas J. Ashby, Pedro Diaz, Marcelo Cintra
KDD
2004
ACM
145views Data Mining» more  KDD 2004»
16 years 1 months ago
Mining coherent gene clusters from gene-sample-time microarray data
Extensive studies have shown that mining microarray data sets is important in bioinformatics research and biomedical applications. In this paper, we explore a novel type of genesa...
Daxin Jiang, Jian Pei, Murali Ramanathan, Chun Tan...