Instruction set simulators are common tools used for the development of new architectures and embedded software among countless other functions. This paper presents a framework th...
In this paper we present an exhaustive evaluation of the memory subsystem in a chip-multiprocessor (CMP) architecture composed of 16 cores. The characterization is performed making...
In our previous work [1], Full Duplex Switched Ethernet was put forward as an attractive candidate to replace the MIL-STD 1553B data bus, in next generation "1553B"embedd...
Ahlem Mifdaoui, Fabrice Frances, Christian Fraboul
In this paper we propose a hybrid FPGA using nanoscale clusters with an architecture similar to clusters of traditional CMOS FPGAs. The proposed cluster is made of a crossbar of n...
—Multiple processors or multi-core CPUs are now in common, and the number of processes running concurrently is increasing in a cluster. Each process issues contiguous I/O request...