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CODES
2006
IEEE
15 years 7 months ago
System-level power-performance trade-offs in bus matrix communication architecture synthesis
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
DASC
2006
IEEE
15 years 7 months ago
Thermal-Aware Task Scheduling to Minimize Energy Usage of Blade Server Based Datacenters
Blade severs are being increasingly deployed in modern datacenters due to their high performance/cost ratio and compact size. In this study, we document our work on blade server b...
Qinghui Tang, Sandeep K. S. Gupta, Daniel Stanzion...
DATE
2006
IEEE
84views Hardware» more  DATE 2006»
15 years 7 months ago
Vulnerability analysis of L2 cache elements to single event upsets
Memory elements are the most vulnerable system component to soft errors. Since memory elements in cache arrays consume a large fraction of the die in modern microprocessors, the p...
Hossein Asadi, Vilas Sridharan, Mehdi Baradaran Ta...
ICDCS
2006
IEEE
15 years 7 months ago
Stable and Accurate Network Coordinates
Network coordinates provide a scalable way to estimate latencies among large numbers of hosts. While there are several algorithms for producing coordinates, none account for the f...
Jonathan Ledlie, Peter R. Pietzuch, Margo I. Seltz...
ICNP
2006
IEEE
15 years 7 months ago
Characterizing and Mitigating Inter-domain Policy Violations in Overlay Routes
— The Internet is a complex structure arising from the interconnection of numerous autonomous systems (AS), each exercising its own administrative policies to reflect the commer...
Srinivasan Seetharaman, Mostafa H. Ammar
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