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» Evaluation of Parallel Logic Simulation Using DVSIM
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IPPS
2007
IEEE
15 years 3 months ago
Performance Evaluation of two Parallel Programming Paradigms Applied to the Symplectic Integrator Running on COTS PC Cluster
There are two popular parallel programming paradigms available to high performance computing users such as engineering and physics professionals: message passing and distributed s...
Lorena B. C. Passos, Gerson H. Pfitscher, Tarcisio...
102
Voted
ICPP
2006
IEEE
15 years 3 months ago
Scalable Time-Parallelization of Molecular Dynamics Simulations in Nano Mechanics
— Molecular Dynamics (MD) is an important atomistic simulation technique, with widespread use in computational chemistry, biology, and materials. An important limitation of MD is...
Yanan Yu, Ashok Srinivasan, Namas Chandra
QEST
2008
IEEE
15 years 3 months ago
ProbDiVinE-MC: Multi-core LTL Model Checker for Probabilistic Systems
We present a new version of PROBDIVINE – a parallel tool for verification of probabilistic systems against properties formulated in linear temporal logic. Unlike the previous r...
Jiri Barnat, Lubos Brim, Ivana Cerná, Milan...
EUROPAR
2001
Springer
15 years 2 months ago
Execution Latency Reduction via Variable Latency Pipeline and Instruction Reuse
Operand bypass logic might be one of the critical structures for future microprocessors to achieve high clock speed. The delay of the logic imposes the execution time budget to be ...
Toshinori Sato, Itsujiro Arita
61
Voted
ISVLSI
2005
IEEE
124views VLSI» more  ISVLSI 2005»
15 years 3 months ago
Boost Logic: A High Speed Energy Recovery Circuit Family
In this paper, we propose Boost Logic, a logic family which relies on voltage scaling, gate overdrive and energy recovery techniques to achieve high energy efficiency at frequenc...
Visvesh S. Sathe, Marios C. Papaefthymiou, Conrad ...