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» Evaluation of Parallel Logic Simulation Using DVSIM
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HPCA
2007
IEEE
16 years 1 days ago
HARD: Hardware-Assisted Lockset-based Race Detection
The emergence of multicore architectures will lead to an increase in the use of multithreaded applications that are prone to synchronization bugs, such as data races. Software sol...
Pin Zhou, Radu Teodorescu, Yuanyuan Zhou
ISCA
2010
IEEE
185views Hardware» more  ISCA 2010»
15 years 4 months ago
Dynamic warp subdivision for integrated branch and memory divergence tolerance
SIMD organizations amortize the area and power of fetch, decode, and issue logic across multiple processing units in order to maximize throughput for a given area and power budget...
Jiayuan Meng, David Tarjan, Kevin Skadron
ICPP
2006
IEEE
15 years 5 months ago
Data Sharing Pattern Aware Scheduling on Grids
These days an increasing number of applications, especially in science and engineering, are dealing with a massive amount of data; hence they are dataintensive. Bioinformatics, da...
Young Choon Lee, Albert Y. Zomaya
SPAA
2006
ACM
15 years 5 months ago
Modeling instruction placement on a spatial architecture
In response to current technology scaling trends, architects are developing a new style of processor, known as spatial computers. A spatial computer is composed of hundreds or eve...
Martha Mercaldi, Steven Swanson, Andrew Petersen, ...
CLOUD
2010
ACM
15 years 4 months ago
RACS: a case for cloud storage diversity
The increasing popularity of cloud storage is leading organizations to consider moving data out of their own data centers and into the cloud. However, success for cloud storage pr...
Hussam Abu-Libdeh, Lonnie Princehouse, Hakim Weath...