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» Evaluation of Parallel Logic Simulation Using DVSIM
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CODES
2005
IEEE
15 years 5 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
ICPP
2009
IEEE
15 years 6 months ago
Bank-aware Dynamic Cache Partitioning for Multicore Architectures
Abstract—As Chip-Multiprocessor systems (CMP) have become the predominant topology for leading microprocessors, critical components of the system are now integrated on a single c...
Dimitris Kaseridis, Jeffrey Stuecheli, Lizy K. Joh...
EUROPAR
2009
Springer
15 years 6 months ago
Adaptive Peer Sampling with Newscast
Abstract. The peer sampling service is a middleware service that provides random samples from a large decentralized network to support gossip-based applications such as multicast, ...
Norbert Tölgyesi, Márk Jelasity
ICDCS
2007
IEEE
15 years 6 months ago
mTreebone: A Hybrid Tree/Mesh Overlay for Application-Layer Live Video Multicast
Application-layer overlay networks have recently emerged as a promising solution for live media multicast on the Internet. A tree is probably the most natural structure for a mult...
Feng Wang, Yongqiang Xiong, Jiangchuan Liu
ICDCS
2006
IEEE
15 years 5 months ago
ASAP: an AS-Aware Peer-Relay Protocol for High Quality VoIP
Peer-to-peer (P2P) technology has been successfully applied in Internet telephony or Voice over Internet Protocol (VoIP), such as the Skype system, where P2P is used for both sear...
Shansi Ren, Lei Guo, Xiaodong Zhang