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» Evaluation of Parallel Logic Simulation Using DVSIM
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CF
2010
ACM
15 years 8 months ago
On-chip communication and synchronization mechanisms with cache-integrated network interfaces
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
Stamatis G. Kavadias, Manolis Katevenis, Michail Z...
PODC
1997
ACM
15 years 7 months ago
Lazy Consistency Using Loosely Synchronized Clocks
Thispaperdescribesanewschemeforguaranteeingthattransactions in a client/server system observe consistent state while they are running. The scheme is presented in conjunction with ...
Atul Adya, Barbara Liskov
BMCBI
2010
132views more  BMCBI 2010»
15 years 3 months ago
Parallel multiplicity and error discovery rate (EDR) in microarray experiments
Background: In microarray gene expression profiling experiments, differentially expressed genes (DEGs) are detected from among tens of thousands of genes on an array using statist...
Wayne Wenzhong Xu, Clay J. Carter
148
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CLUSTER
2009
IEEE
15 years 1 months ago
MITHRA: Multiple data independent tasks on a heterogeneous resource architecture
With the advent of high-performance COTS clusters, there is a need for a simple, scalable and faulttolerant parallel programming and execution paradigm. In this paper, we show that...
Reza Farivar, Abhishek Verma, Ellick Chan, Roy H. ...
ICALP
2009
Springer
16 years 3 months ago
LTL Path Checking Is Efficiently Parallelizable
We present an AC1 (logDCFL) algorithm for checking LTL formulas over finite paths, thus establishing that the problem can be efficiently parallelized. Our construction provides a f...
Lars Kuhtz, Bernd Finkbeiner