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» Evaluation of Parallel Logic Simulation Using DVSIM
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ICCAD
2002
IEEE
94views Hardware» more  ICCAD 2002»
16 years 2 days ago
High-level synthesis of distributed logic-memory architectures
Abstract— With the increasing cost of global communication onchip, high-performance designs for data-intensive applications require architectures that distribute hardware resourc...
Chao Huang, Srivaths Ravi, Anand Raghunathan, Nira...
ISCA
1994
IEEE
117views Hardware» more  ISCA 1994»
15 years 7 months ago
Evaluating Stream Buffers as a Secondary Cache Replacement
Today's commodity microprocessors require a low latency memory system to achieve high sustained performance. The conventional high-performance memory system provides fast dat...
Subbarao Palacharla, Richard E. Kessler
HPCA
1996
IEEE
15 years 7 months ago
Fault-Tolerance with Multimodule Routers
The current multiprocessors such asCray T3D support interprocessor communication using partitioned dimension-order routers (PDRs). In a PDR implementation, the routing logic and sw...
Suresh Chalasani, Rajendra V. Boppana
CCGRID
2002
IEEE
15 years 8 months ago
User-Centric Performance Analysis of Market-Based Cluster Batch Schedulers
This paper presents a performance analysis of marketbased batch schedulers for clusters of workstations. In contrast to previous work, we use user-centric performance metrics as t...
Brent N. Chun, David E. Culler
DDECS
2007
IEEE
143views Hardware» more  DDECS 2007»
15 years 9 months ago
An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques
Logic Soft Errors caused by radiation are a major concern when working with circuits that need to operate in harsh environments, such as space or avionics applications, where soft ...
Oscar Ruano, Pilar Reyes, Juan Antonio Maestro, Lu...