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IPPS
2010
IEEE
14 years 9 months ago
Performance modeling of heterogeneous systems
Predicting how well applications may run on modern systems is becoming increasingly challenging. It is no longer sufficient to look at number of floating point operations and commu...
Jan Christian Meyer, Anne C. Elster
107
Voted
IPPS
2010
IEEE
14 years 9 months ago
Adapting cache partitioning algorithms to pseudo-LRU replacement policies
Abstract-- Recent studies have shown that cache partitioning is an efficient technique to improve throughput, fairness and Quality of Service (QoS) in CMP processors. The cache par...
Kamil Kedzierski, Miquel Moretó, Francisco ...
CF
2010
ACM
15 years 4 months ago
On-chip communication and synchronization mechanisms with cache-integrated network interfaces
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
Stamatis G. Kavadias, Manolis Katevenis, Michail Z...
HPCA
2009
IEEE
16 years 6 days ago
Dacota: Post-silicon validation of the memory subsystem in multi-core designs
The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules ...
Andrew DeOrio, Ilya Wagner, Valeria Bertacco
90
Voted
VR
2002
IEEE
125views Virtual Reality» more  VR 2002»
15 years 4 months ago
A Scalable, Multi-User VRML Server
VRML97 allows the description of dynamic worlds that can change with both the passage of time, and user interaction. Unfortunately, the current VRML usage model prevents its full ...
Thomas Rischbeck, Paul Watson