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128
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PARELEC
2006
IEEE
15 years 5 months ago
2006
IEEE
We have developed an application-driven methodology for implementing parallel and heterogeneous programmable platforms. We deploy our flow for network access platforms where we h...
101
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IPPS
2007
IEEE
15 years 6 months ago
2007
IEEE
Hardware accelerators are increasingly used to extend the computational capabilities of baseline scalar processors to meet the growing performance and power requirements of embedd...
104
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CCO
2001
Springer
15 years 4 months ago
2001
Springer
Branch, cut, and price (BCP) is an LP-based branch and bound technique for solving large-scale discrete optimization problems (DOPs). In BCP, both cuts and variables can be generat...
IPPS
2006
IEEE
15 years 5 months ago
2006
IEEE
This paper presents the hardware architecture of DynaCORE, a dynamically reconfigurable system-on-chip for network applications. DynaCORE is an application specific coprocessor ...
104
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ISCA
1993
IEEE
15 years 3 months ago
1993
IEEE
Parallel programs that use critical sections and are executed on a shared-memory multiprocessor with a writeinvalidate protocol result in invalidation actions that could be elimin...