3893 search results - page 633 / 779 » Execution Architectures and Compilation |
193
click to vote
ISCA
2012
IEEE
13 years 7 months ago
2012
IEEE
The reliability of future processors is threatened by decreasing transistor robustness. Current architectures focus on delivering high performance at low cost; lifetime device rel...
123
click to vote
DAC
2009
ACM
16 years 6 months ago
2009
ACM
Post-silicon processor debugging is frequently carried out in a loop consisting of several iterations of the following two key steps: (i) processor execution for some duration, fo...
132
click to vote
DAC
2008
ACM
16 years 5 months ago
2008
ACM
Scenario-based design exploits the time-varying execution behavior of applications by dynamically adapting the system on which they run. This is a particularly interesting design ...
117
click to vote
HPCA
2008
IEEE
16 years 5 months ago
2008
IEEE
Hard-to-predict branches depending on longlatency cache-misses have been recognized as a major performance obstacle for modern microprocessors. With the widening speed gap between...
149
click to vote
HPCA
2005
IEEE
16 years 5 months ago
2005
IEEE
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...