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FPL
2007
Springer
97views Hardware» more  FPL 2007»
15 years 3 months ago
An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems
Recently, there is a surge of interests in using FPGAs for computer architecture research including applications from emulating and analyzing a new platform to accelerating microa...
Taeweon Suh, Shih-Lien Lu, Hsien-Hsin S. Lee
GECCO
2006
Springer
206views Optimization» more  GECCO 2006»
15 years 3 months ago
A dynamically constrained genetic algorithm for hardware-software partitioning
In this article, we describe the application of an enhanced genetic algorithm to the problem of hardware-software codesign. Starting from a source code written in a high-level lan...
Pierre-André Mudry, Guillaume Zufferey, Gia...
ISLPED
1995
ACM
95views Hardware» more  ISLPED 1995»
15 years 3 months ago
Reducing the frequency of tag compares for low power I-cache design
In current processors, the cache controller, which contains the cache directory and other logic such as tag comparators, is active for each instruction fetch and is responsible fo...
Ramesh Panwar, David A. Rennels
FASE
2008
Springer
15 years 1 months ago
Language-Based Optimisation of Sensor-Driven Distributed Computing Applications
In many distributed computing paradigms, especially sensor networks and ubiquitous computing but also grid computing and web services, programmers commonly tie their application to...
Jonathan J. Davies, Alastair R. Beresford, Alan My...
ISMB
1993
15 years 1 months ago
Protein Sequencing Experiment Planning Using Analogy
Experiment design and execution is a central activity in the natural sciences. The SeqERsystem provides a general architecture for the integration of automated planning techniques...
Brian P. Kettler, Lindley Darden