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» Experiences with the DEVStone benchmark
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80
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ICRA
2006
IEEE
114views Robotics» more  ICRA 2006»
15 years 6 months ago
Multi-level Free-space Dilation for Sampling narrow Passages in PRM Planning
— Free-space dilation is an effective approach for narrow passage sampling, a well-recognized difficulty in probabilistic roadmap (PRM) planning. Key to this approach are method...
David Hsu, Gildardo Sánchez-Ante, Ho-Lun Ch...
93
Voted
IPPS
2006
IEEE
15 years 6 months ago
Placement and routing of Boolean functions in constrained FPGAs using a distributed genetic algorithm and local search
In this work we present a system for implementing the placement and routing stages in the FPGA cycle of design, into the physical design stage. We start with the ISCAS benchmarks,...
Manuel Rubio del Solar, Juan Manuel Sánchez...
101
Voted
IPPS
2006
IEEE
15 years 6 months ago
On-the-fly kernel updates for high-performance computing clusters
High-performance computing clusters running longlived tasks currently cannot have kernel software updates applied to them without causing system downtime. These clusters miss oppo...
Kristis Makris, Kyung Dong Ryu
88
Voted
IROS
2006
IEEE
233views Robotics» more  IROS 2006»
15 years 6 months ago
Machine-mediated Motor Skill Training Method in Haptic-enabled Chinese Handwriting Simulation System
Training of motor skill through machine-mediated method is a promising way to improve complex dexterous manipulation skill. New method of fusion between human motor skill and machi...
Dangxiao Wang, Yuru Zhang, Chong Yao
96
Voted
ISQED
2006
IEEE
90views Hardware» more  ISQED 2006»
15 years 6 months ago
Transaction Level Error Susceptibility Model for Bus Based SoC Architectures
System on Chip architectures have traditionally relied upon bus based interconnect for their communication needs. However, increasing bus frequencies and the load on the bus calls...
Ing-Chao Lin, Suresh Srinivasan, Narayanan Vijaykr...