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» Exploiting Architecture in Experimental System Development
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VLSID
2008
IEEE
150views VLSI» more  VLSID 2008»
15 years 10 months ago
PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors
Simultaneous Multi-Threading (SMT) processors are becoming popular because they exploit both instruction-level and threadlevel parallelism by issuing instructions from different t...
Deepa Kannan, Aseem Gupta, Aviral Shrivastava, Nik...
PC
2010
190views Management» more  PC 2010»
14 years 8 months ago
High-performance cone beam reconstruction using CUDA compatible GPUs
Compute unified device architecture (CUDA) is a software development platform that allows us to run C-like programs on the nVIDIA graphics processing unit (GPU). This paper prese...
Yusuke Okitsu, Fumihiko Ino, Kenichi Hagihara
SIGMETRICS
2011
ACM
229views Hardware» more  SIGMETRICS 2011»
14 years 14 days ago
Model-driven optimization of opportunistic routing
Opportunistic routing aims to improve wireless performance by exploiting communication opportunities arising by chance. A key challenge in opportunistic routing is how to achieve ...
Eric Rozner, Mi Kyung Han, Lili Qiu, Yin Zhang
53
Voted
DAC
2009
ACM
15 years 10 months ago
On systematic illegal state identification for pseudo-functional testing
The discrepancy between integrated circuits' activities in normal functional mode and that in structural test mode has an increasing adverse impact on the effectiveness of ma...
Feng Yuan, Qiang Xu
93
Voted
DAC
2009
ACM
15 years 10 months ago
A DVS-based pipelined reconfigurable instruction memory
Energy consumption is of significant concern in battery operated embedded systems. In the processors of such systems, the instruction cache consumes a significant fraction of the ...
Zhiguo Ge, Tulika Mitra, Weng-Fai Wong