94 search results - page 5 / 19 » Exploiting Speculative Thread-Level Parallelism on a SMT Pro... |
83
Voted
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
Instruction Level Parallelism (ILP) extraction for multicluster VLIW processors is a very hard task. In this paper, we propose a retargetable architecture that can exploit ILP and...
ISCAPDCS
2003
14 years 10 months ago
2003
This paper presents the Dynamic Simultaneous Multithreaded Architecture (DSMT). DSMT efficiently executes multiple threads from a single program on a SMT processor core. To accomp...
104
click to vote
PPOPP
2006
ACM
15 years 3 months ago
2006
ACM
As multi-core architectures with Thread-Level Speculation (TLS) are becoming better understood, it is important to focus on TLS compilation. TLS compilers are interesting in that,...
IPPS
2010
IEEE
14 years 7 months ago
2010
IEEE
With the shrinking of transistors continuing to follow Moore's Law and the non-scalability of conventional outof-order processors, multi-core systems are becoming the design ...
87
Voted
ASPLOS
2006
ACM
15 years 3 months ago
2006
ACM
Exploiting thread level parallelism is paramount in the multi-core era. Transactions enable programmers to expose such parallelism by greatly simplifying the multi-threaded progra...