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» Exploring Design Space of VLIW Architectures
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ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
14 years 12 months ago
Translation caching: skip, don't walk (the page table)
This paper explores the design space of MMU caches that accelerate virtual-to-physical address translation in processor architectures, such as x86-64, that use a radix tree page t...
Thomas W. Barr, Alan L. Cox, Scott Rixner
IPPS
2007
IEEE
15 years 4 months ago
Towards Optimal Multi-level Tiling for Stencil Computations
Stencil computations form the performance-critical core of many applications. Tiling and parallelization are two important optimizations to speed up stencil computations. Many til...
Lakshminarayanan Renganarayanan, Manjukumar Harthi...
HPCA
2003
IEEE
15 years 10 months ago
A Statistically Rigorous Approach for Improving Simulation Methodology
Due to cost, time, and flexibility constraints, simulators are often used to explore the design space when developing a new processor architecture, as well as when evaluating the ...
Joshua J. Yi, David J. Lilja, Douglas M. Hawkins
DATE
2006
IEEE
195views Hardware» more  DATE 2006»
15 years 4 months ago
Application specific instruction processor based implementation of a GNSS receiver on an FPGA
In this paper the concept of a reconfigurable hardware macro to be used as a generic building block in lowpower, low-cost SoC for multioperable GNSS positioning is described, feat...
Götz Kappen, Tobias G. Noll
SAT
2010
Springer
158views Hardware» more  SAT 2010»
15 years 1 months ago
Dynamic Scoring Functions with Variable Expressions: New SLS Methods for Solving SAT
Abstract. We introduce a new conceptual model for representing and designing Stochastic Local Search (SLS) algorithms for the propositional satisfiability problem (SAT). Our model...
Dave A. D. Tompkins, Holger H. Hoos