Sciweavers

546 search results - page 68 / 110
» Extended Null-Move Reductions
Sort
View
DATE
2008
IEEE
145views Hardware» more  DATE 2008»
15 years 4 months ago
Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures
We present a novel methodology for design space exploration using a two-steps scheme to optimize the number of virtual channel buffers (buffers take the premier share of the route...
Mohammad Abdullah Al Faruque, Jörg Henkel
IEEEPACT
2008
IEEE
15 years 4 months ago
Scalable and reliable communication for hardware transactional memory
In a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true ...
Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen ...
MICRO
2007
IEEE
129views Hardware» more  MICRO 2007»
15 years 4 months ago
A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy
Current on-chip block-centric memory hierarchies exploit access patterns at the fine-grain scale of small blocks. Several recently proposed techniques for coherence traffic reduct...
Jason Zebchuk, Elham Safi, Andreas Moshovos
GEOINFORMATICA
1998
125views more  GEOINFORMATICA 1998»
14 years 9 months ago
Computational Perspectives on Map Generalization
ally related entity types, or classes, into higher level, more abstract types, as part of a hierarchical classi®cation scheme. graphy, generalization retains the notion of abstrac...
Robert Weibel, Christopher B. Jones
JUCS
2010
117views more  JUCS 2010»
14 years 8 months ago
NP-completeness and FPT Results for Rectilinear Covering Problems
Abstract: This paper discusses three rectilinear (that is, axis-parallel) covering problems in d dimensions and their variants. The first problem is the Rectilinear Line Cover whe...
Vladimir Estivill-Castro, Apichat Heednacram, Fran...