We present a novel methodology for design space exploration using a two-steps scheme to optimize the number of virtual channel buffers (buffers take the premier share of the route...
In a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true ...
Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen ...
Current on-chip block-centric memory hierarchies exploit access patterns at the fine-grain scale of small blocks. Several recently proposed techniques for coherence traffic reduct...
ally related entity types, or classes, into higher level, more abstract types, as part of a hierarchical classi®cation scheme. graphy, generalization retains the notion of abstrac...
Abstract: This paper discusses three rectilinear (that is, axis-parallel) covering problems in d dimensions and their variants. The first problem is the Rectilinear Line Cover whe...
Vladimir Estivill-Castro, Apichat Heednacram, Fran...