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ISLPED
2004
ACM
149views Hardware» more  ISLPED 2004»
15 years 11 months ago
Creating a power-aware structured ASIC
In an attempt to enable the cost-effective production of lowand mid-volume application-specific chips, researchers have proposed a number of so-called structured ASIC architectur...
R. Reed Taylor, Herman Schmit
COMPSAC
2002
IEEE
15 years 10 months ago
The Architecture of a Dynamically Updatable, Component-Based System
On-the-fly replacement of software may require simultanous distributed updates of components. If an update changes some interfaces or protocols, the update must be performed in a...
Robert Pawel Bialek
FPL
2005
Springer
98views Hardware» more  FPL 2005»
15 years 11 months ago
Using DSP Blocks For ROM Replacement: A Novel Synthesis Flow
This paper describes a method based on polynomial approximation for transferring ROM resources used in FPGA designs to multiplication and addition operations. The technique can be...
Gareth W. Morris, George A. Constantinides, Peter ...
ARC
2006
Springer
157views Hardware» more  ARC 2006»
15 years 9 months ago
PISC: Polymorphic Instruction Set Computers
We introduce a new paradigm in the computer architecture referred to as Polymorphic Instruction Set Computers (PISC). This new paradigm, in difference to RISC/CISC, introduces hard...
Stamatis Vassiliadis, Georgi Kuzmanov, Stephan Won...
RSP
2003
IEEE
149views Control Systems» more  RSP 2003»
15 years 11 months ago
Rapid Scheduling of Efficient VLSI Architectures for Next-Generation HSDPA
In this paper, an efficient design flow integrating Mentor Graphics Precesion C and HDL designer is derived. In this hybrid prototyping environment, efficient FPGA architectures a...
Yuanbin Guo, Gang Xu, Dennis McCain, Joseph R. Cav...