Sciweavers

4155 search results - page 90 / 831
» External Memory Algorithms
Sort
View
ISCA
1989
IEEE
109views Hardware» more  ISCA 1989»
15 years 6 months ago
Improving Performance of Small On-Chip Instruction Caches
Most current single-chip processors employ an on-chip instruction cache to improve performance. A miss in this insk-uction cache will cause an external memory reference which must...
Matthew K. Farrens, Andrew R. Pleszkun
162
Voted
ECRTS
2007
IEEE
15 years 8 months ago
WCET-Directed Dynamic Scratchpad Memory Allocation of Data
Many embedded systems feature processors coupled with a small and fast scratchpad memory. To the difference with caches, allocation of data to scratchpad memory must be handled by...
Jean-François Deverge, Isabelle Puaut
IPPS
2010
IEEE
15 years 11 days ago
MMT: Exploiting fine-grained parallelism in dynamic memory management
Dynamic memory management is one of the most expensive but ubiquitous operations in many C/C++ applications. Additional features such as security checks, while desirable, further w...
Devesh Tiwari, Sanghoon Lee, James Tuck, Yan Solih...
DAC
2012
ACM
13 years 4 months ago
Run-time power-down strategies for real-time SDRAM memory controllers
Powering down SDRAMs at run-time reduces memory energy consumption significantly, but often at the cost of performance. If employed speculatively with real-time memory controller...
Karthik Chandrasekar 0001, Benny Akesson, Kees Goo...
ACL
2000
15 years 3 months ago
Memory-Efficient and Thread-Safe Quasi-Destructive Graph Unification
In terms of both speed and memory consumption, graph unification remains the most expensive component of unification-based grammar parsing. We present a technique to reduce the me...
Marcel P. van Lohuizen