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IPPS
2008
IEEE
15 years 9 months ago
Automatic generation of a parallel sorting algorithm
In this paper, we discuss a library generator for parallel sorting routines that examines the input characteristics (and the parameters they affect) to select the best performing ...
Brian A. Garber, Daniel Hoeflinger, Xiaoming Li, M...
125
Voted
ICPPW
2002
IEEE
15 years 7 months ago
Near-Optimal Loop Tiling by Means of Cache Miss Equations and Genetic Algorithms
The effectiveness of the memory hierarchy is critical for the performance of current processors. The performance of the memory hierarchy can be improved by means of program transf...
Jaume Abella, Antonio González, Josep Llosa...
JCP
2008
135views more  JCP 2008»
15 years 2 months ago
Hybrid Evolutionary Algorithm Based Solution for Register Allocation for Embedded Systems
Embedded systems have an ever-increasing need for optimizing compilers to produce high quality codes with a limited general purpose register set. Either memory or registers are use...
Anjali Mahajan, M. S. Ali
ICCAD
2005
IEEE
130views Hardware» more  ICCAD 2005»
15 years 11 months ago
A cache-defect-aware code placement algorithm for improving the performance of processors
— Yield improvement through exploiting fault-free sections of defective chips is a well-known technique [1][2]. The idea is to partition the circuitry of a chip in a way that fau...
Tohru Ishihara, Farzan Fallah
119
Voted
EDBT
2008
ACM
135views Database» more  EDBT 2008»
16 years 2 months ago
Minimizing latency and memory in DSMS: a unified approach to quasi-optimal scheduling
Data Stream Management Systems (DSMSs) must support optimized execution scheduling of multiple continuous queries on massive, and frequently bursty, data streams. Previous approac...
Yijian Bai, Carlo Zaniolo