353 search results - page 28 / 71 » FPGA architecture characterization for system level performa... |
ICCAD
2002
IEEE
15 years 6 months ago
2002
IEEE
As the scale of system integration continues to grow, the on-chip communication becomes the ultimate bottleneck of system performance and the primary determinant of system archite...
JUCS
2000
14 years 9 months ago
2000
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
PPOPP
2006
ACM
15 years 3 months ago
2006
ACM
This work presents a general methodology for estimating the performance of an HPC workload when running on a future hardware architecture. Further, it demonstrates the methodology...
MVA
1992
14 years 11 months ago
1992
In this work the Low Level Vision Unit (LLVU) of the Heterogeneous and Reconfigurable Machine for Image Analysis (HERMIA) is described. The LLVU consists of the innovative integra...
104
click to vote
IISWC
2008
IEEE
15 years 4 months ago
2008
IEEE
—High-speed content inspection of network traffic is an important new application area for programmable networking systems, and has recently led to several proposals for high-per...