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120
Voted
ITC
2003
IEEE
162views Hardware» more  ITC 2003»
15 years 9 months ago
FPGA Interconnect Delay Fault Testing
The interconnection network consumes the majority of die area in an FPGA. Presented is a scalable manufacturing test method for all SRAM-based FPGAs, able to detect multiple inter...
Erik Chmelar
110
Voted
FCCM
2002
IEEE
114views VLSI» more  FCCM 2002»
15 years 8 months ago
Implementing a Simple Continuous Speech Recognition System on an FPGA
Speech recognition is a computationally demanding task, particularly the stage which uses Viterbi decoding for converting pre-processed speech data into words or sub-word units. W...
Stephen J. Melnikoff, Steven F. Quigley, Martin J....
145
Voted
DATE
2009
IEEE
141views Hardware» more  DATE 2009»
15 years 7 months ago
Evaluation on FPGA of triple rail logic robustness against DPA and DEMA
Side channel attacks are known to be efficient techniques to retrieve secret data. In this context, this paper concerns the evaluation of the robustness of triple rail logic agains...
Victor Lomné, Philippe Maurine, Lionel Torr...
124
Voted
DATE
2004
IEEE
149views Hardware» more  DATE 2004»
15 years 7 months ago
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
This paper describes a novel design methodology to implement a secure DPA resistant crypto processor. The methodology is suitable for integration in a common automated standard ce...
Kris Tiri, Ingrid Verbauwhede
157
Voted
FPL
2006
Springer
135views Hardware» more  FPL 2006»
15 years 7 months ago
FPGA Design Considerations in the Implementation of a Fixed-Throughput Sphere Decoder for MIMO Systems
A field-programmable gate array (FPGA) implementation of a new detection algorithm for uncoded multiple inputmultiple output (MIMO) systems based on the complex version of the sph...
Luis G. Barbero, John S. Thompson