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CHES
2007
Springer
165views Cryptology» more  CHES 2007»
15 years 10 months ago
FPGA Intrinsic PUFs and Their Use for IP Protection
In recent years, IP protection of FPGA hardware designs has become a requirement for many IP vendors. In [34], Simpson and Schaumont proposed a fundamentally different approach to...
Jorge Guajardo, Sandeep S. Kumar, Geert Jan Schrij...
125
Voted
APCCAS
2006
IEEE
227views Hardware» more  APCCAS 2006»
15 years 10 months ago
FPGA Prototyping of Spatio-temporal 2D IIR Broadband Beam Plane-wave Filters
— We propose a VLSI architecture for the single-chip realization of 2D spatio-temporal IIR digital filters, consisting of a meshed connection of concurrent identical vector-proce...
Arjuna Madanayake, Leonard T. Bruton
130
Voted
CCECE
2006
IEEE
15 years 10 months ago
Reconfigurable Implementation of Wavelet Transform on an Fpga-Augmented NIOS Processor
The wavelet transform is a very popular tool in engineering for signal analysis. With respect to image compression, the new JPEG 2000 image standard incorporates wavelet transform...
Eugene Hyun, Mihai Sima, Michael McGuire
141
Voted
ITCC
2005
IEEE
15 years 9 months ago
FPGA Implementations of the ICEBERG Block Cipher
— This paper presents FPGA (Field Programmable Gate Array) implementations of ICEBERG, a block cipher designed for reconfigurable hardware implementations and presented at FSE 2...
François-Xavier Standaert, Gilles Piret, Ga...
CHES
2005
Springer
146views Cryptology» more  CHES 2005»
15 years 9 months ago
AES on FPGA from the Fastest to the Smallest
Two new FPGA designs for the Advanced Encryption Standard (AES) are presented. The first is believed to be the fastest, achieving 25 Gbps throughput using a Xilinx Spartan-III (XC3...
Tim Good, Mohammed Benaissa